Michael A Rappa.

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WORKING PAPER
ALFRED P. SLOAN SCHOOL OF MANAGEMENT



OBSTACLES TO SYSTEMIC INNOVATION:

AN ILLUSTRATION FROM SEMICONDUCTOR

MANUFACTURING TECHNOLOGY



.^



Michael A. Rappa

Massachusetts Institute of Technology



31 August 1993



Sloan WP# 3605-93



MASSACHUSETTS

INSTITUTE OF TECHNOLOGY

50 MEMORIAL DRIVE

CAMBRIDGE, MASSACHUSETTS 02139




z!Massachusetts Institute of Technology



OBSTACLES TO SYSTEMIC INNOVATION:

AN ILLUSTRATION FROM SEMICONDUCTOR

MANUFACTURING TECHNOLOGY

Michael A. Rappa

Massachusetts Institute of Technology



.J



31 August 1993



Sloan WP # 3605-93



1993 MASSACHUSETTS INSTITUTE OF TECHNOLOGY



Massachusetts Institute of Technology

Alfred P. Sloan School of Management

50 Memorial Drive, E52-538

Cambridge, MA 02139



Obstacles to Systemic Innovation: An Illustration from
Semiconductor Manufacturing Technology

Michael A. Rappa
Massachusetts Institute of Technology



Microenvironment technology holds significant potential for enabling the cost-
effective production of semiconductor integrated circuits. However, integrated
circuit manufacturers have been reluctant to adopt the technology even though
there is substantial empirical evidence of its effectiveness. This paper suggests that
the slow acceptance of microenvironment technology can be understood in terms
of its weak appropriability and systemic nature.



I. INTRODUCTION

The history of semiconductor technology has been aptly called a "revolution in
miniature" (Braun and Macdonald, 1978). This is because the principal goal,
miniaturization, is to design circuits with the thinnest possible line widths, thereby
permitting the greatest possible degree of circuit integration on a single chip. The
sophistication of semiconductors today is attributable in large part to the success of
scientists and engineers in pushing line features to their physical limits. During the
past decade, the feature sizes of dynamic random access memory (DRAM) chips
have been reduced from 2.5)J.m for 64-kilobit devices to 0.5|Im for l6-megabit
devices. According to the Semiconductor Industry Association, future generations
of DRAMs will have less than one-half micron feature sizes (see Table 1).

The relationship between line geometry and circuit density places stringent
demands on the manufacturing discipline necessary to meet the tolerances of sub-
micron devices. Particle contamination during wafer processing, in particular, can
cause defects on the wafer surface that have a substantial effect on reducing chip
yield. Figure 1 illustrates the empirical relationship between the number of defects
per square centimeter on a wafer and test yield for l6-megabit DRAM wafer
processing.

TABLE 1
Projected Trend in DRAM Integrated Circuit Complexity











Year








1992


1995


1998


2001


2004


2007


Feature size (|Im)


0.5


0.35


0.25


0.18


0.12


0.10


Gates per chip


300K


800K


2M


5M


lOM


20M


Bits per chip


16M


64M


256M


IG


4G


16G


Chip size (mm )


132


200


320


500


700


1000



Source: Semiconduaor Industry Association, March 1993



Michael A. Rap pa



3

z




25 50 75

Test yield (%)



100



Fig. 1. Relationship between defect density and test yield for 16-megabit DRAMs
(Castrucci and Dickerson, 1988)

As line widths shrink, particles that were previously insignificant become
detrimental. Typically, particles more than one-tenth of the size of the smallest
critical feature on a chip can cause defects (King 1991). Research by the Institute
for Microcontamination Control suggests that processing a wafer with 1.0|Im line
widths under the same conditions as one with 2.5|Hm line widths will result in a
sixfold increase in "killer" particles — that is, particles that reduce manufacturing
yield — due to the geometry-related effects alone (Burnett, 1988; Gall, 1990). The
problem of submicron wafer processing will become all the more severe because
physical forces at the surface of the wafer make it virtually impossible to remove
the smallest particles.

The trend in design geometry means that wafer processing must be conducted
in an increasingly cleaner environment. This is done by performing wafer process-
ing in elaborate "cleanrooms" where the ambient is carefully controlled to reduce
the number of minute particles. However, as the need for cleanliness has increased,
the use of cleanrooms has become more costly. The present cost of constructing a
state-of-the-art cleanroom for wafer processing can be as much as $1500 per square
foot (Dicken, 1990; Sayre et al., 1989). Figure 2 shows the dramatic growth in the
overall cost of building and equipping a half-micron DRAM facility, which some
manufacturers anticipate may exceed $350 million by the mid-1990s.

The stricter requirements for cleanliness and the escalating cost of cleanrooms,
may induce some IC manufacturers to adopt "microenvironment" technologies as
an alternative solution to the problem of contamination in wafer processing.' The



The concept of microenvironment technology has been given several labels, including "wafer
isolation technologies," "local cleanrooms," and "minienvironments."" The acronym SMIF —
which stands for Standard Mechanical Interface — is a common term first used by Hewlett-Packard,
the originator of the concept, and later employed in the trademarks of Asyst Technologies, the
commercial pioneer of the technology. To maintain consistency, this paper will use the term
"microenvironment " as an encompassing concept, while reserving SMIF to signify Asyst-related
technology in particular.



obstacles to Systemic Innovation 3

idea behind microenvironment technology is to isolate the environment immedi-
ately surrounding the wafer during processing and storage, maintaining this rather
limited area — and only this area — in an ultra-clean state. This differs significantly
from conventional cleanrooms, in which the entire wafer processing facility — tools,
operators, and wafers — -is maintained in an ultra-clean state.



o
-a




2.0 1,8 1.6 1.4 1.2 I.O 0.8 0.6 0.4
Resolution (|im)

Fig. 2. Increasing cost of advanced semiconductor manufacturing facilities,
assuming 800 150mm wafer starts per day (Toiliver, 1991).



In essence, microenvironment technology is a wafer transport and storage sys-
tem consisting of an integrated collection of robotics, automation techniques, tool
enclosures, and wafer "pods" that are used to maintain the wafers in a Class 1 (i.e.,
one 0.5|J.m particle per cubic foot) ambient. Even so, it is not an especially com-
plex technology in the usual sense of the term. Indeed, microenvironment technol-
ogy is fairly straightforward in nature. It consists of nothing more than conventional
manufacturing enclosures and robotics for handling and transporting wafers. The
"radical" quality of microenvironment technology is not in its complexity, but in
the way it alters how manufacturers must think about the wafer processing system.

Curiously, even though microenvironment technology is an appealing concept
and the empirical evidence to date supports its effectiveness, its adoption by IC
manufacturers has been very slow. This paper explores why this has been the case. At
the heart of the argument is the idea that as a "systemic innovation," microenviron-
ment technology presents unique obstacles that inhibit the speed of its adoption
among potential users. Before discussing the obstacles to systemic innovation, the
next section examines the problem of contamination control in IC manufacturing
and the conventional approaches toward cleanroom design. Section III provides a
description of microenvironment technology and its rationale, and Section IV
reviews the empirical evidence of its effectiveness in reducing particle contamina-
tion and improving manufacturing yield.



Michael A. Rappa



II. CONTAMINATION CONTROL IN SEMICONDUCTOR MANUFACTURING

The sensitivity of IC fabrication to particle contamination requires that wafer
processing be done under extremely clean conditions. The current guidelines for
cleanliness are governed by Federal Standard 209D issued in 1988 (Moller, 1991).
The standard defines the number of permissible particles per cubic foot of a given
size. The current target levels of air cleanliness for the fabrication of submicron IC
devices are: Class 0.1 (undefined by 209D) for the atmosphere where wafers are
fully exposed; Class 1 for wafers protected in cassettes or enclosed boxes; Class
1000 to Class 10,000 for equipment, technicians, engineering, and operating area —
depending upon the type of wafer transport (King 1991).

Recent research pinpointing the sources of particle contamination in wafer pro-
cessing suggests that equipment operators and the loading and unloading of wafer
cassettes from tools each account for 30% of the contaminants (Dicken 1990).
Another 25% of the contaminants are found in the process tool itself, while 10%
originate in the cleanroom environment and 5% are from the wafer storage cassette.

A tremendous amount of innovative thinking has gone into the design and oper-
ation of cleanrooms. One such innovation, known as "laminar" (or "unidirectional")
airflow, is essential to achieving the level of cleanliness required for wafer process-
ing. This involves the vertical circulation from ceiling to floor of a high volume of
filtered air through the cleanroom. The filters remove 99.97% of the particles,
0.5|im in size or larger. The shower of clean air flowing over the wafer processing
area is very effective in reducing the number ol airborne particles that would other-
wise interfere in the fabrication process.

Another important design innovation is the cleanroom tunnel concept, which
separates the wafer processing areas from the circulation and tool maintenance
areas. This is done by mounting the process tools such that only the bulkhead, where
the operator works, is in the cleanroom tunnel. One advantage of this approach is
that the air flow rate can be reduced outside the critical processing area. Another
benefit is that it enables the extraction of return air laterally into the maintenance
areas.

The tunnel concept, highly efficient air filters, and laminar flow are essential
design elements of cleanrooms for IC wafer processing. Nonetheless, the modern
cleanroom poses certain problems for efficient wafer processing. Providing laminar
airflow, for example, is expensive and especially sensitive to the price of energy.
Given the size of the typical cleanroom tunnel, the air handling requirements are
substantial (about 1620 cubic meters per hour per square meter) and the investment
and operation of air handling units can be quite costly. It is estimated that as much
as 75% of the annual operating cost of a cleanroom is directly related to the cost of
energy (Schicht 1991).

Furthermore, by minimizing the amount of cleanroom area, careful considera-
tion must be given to the design and layout of the facility, equipment footprints,
and material flows. The space constraint means less strategic flexibility to
accommodate changing operational requirements, equipment substitutions, or sub-
stantial layout alterations. In some cases, new equipment with exceptionally large



obstacles to Systemic Innovation 5

footprints, such as cluster tools, may not fit within an existing cleanroom. Even
when equipment changes can be made, production shutdowns of the entire clean-
room facility are often required.

Class 1 cleanrooms will also use cassette-to-cassette wafer transport in order to
eliminate the handling of wafers by operators. Operators will be fully gowned in
cleanroom garments with transparent face helmets. This is of particular concern
since it can significantly effect an operator's productivity and can be very costly.
Not only do garments restrict comfort, each exit and reentry to the cleanroom in
the course of an operator's workday requires a garment change (Toy, 1989).

Given the present trend in IC design geometry, it is clear that the challenge of
contamination control in wafer processing will persist. A crucial question is
whether or not advances in conventional cleanroom design and construction can keep
pace with the needs of submicron technology. Reducing contamination down to a
level of 0.05|J.m particles is non-trivial. Will extending the conventional approach
to cleanroom design be sufficient — and if so, at what cost? Or will it require a
more fundamental change, such as microenvironment technology?



III. RATIONALE FOR MICROENVIRONMENT TECHNOLOGY

The problem by particle contamination in wafer processing presents a serious
challenge to the conventional approach of cleanroom design. The requirements of
Class 1 or Class 0. 1 for half-micron circuit designs will greatly increase the cost,
reduce strategic flexibility, and pose further restrictions on wafer fabrication oper-
ators. Accordingly, the concept of microenvironment technologies may present an
attractive approach to contamination control.

The basic logic behind microenvironment technology is to recognize that only
the area immediately surrounding the wafer — an area that is actually minuscule in
comparison to that of the entire cleanroom — needs to be kept particle-free. Bluntly
stated, the rationale is quite simple: Why put so much effort and money into main-
taining 10,000 square feet of cleanroom at Class 1, when it is only a very small area
that actually affects the level of particle contamination on a wafer? The principal
sources of contaminants are in close proximity to the wafer. Thus, focusing atten-
tion on the area closest to the wafer seems quite logical. Microenvironment tech-
nology does precisely this: it isolates and maintains the immediate area around the
wafers and within tools at a Class 1 level. The rest of the cleanroom environment
can be maintained at Class 1000 or higher.

Hewlett-Packard pioneered the concept of microenvironment technology in the
early 1980s, which it called SMIF, an acronym for "standard mechanical interface".
However, it is a start-up firm, Asyst Technologies, which has been largely respon-
sible for the commercial introduction of SMIF products since 1984. The basic
components of Asyst's system are the SMIF-Pod™, SMIF-Arms™, and equipment
enclosures. A SMIF-Pod is an environmentally secure wafer cassette container that
reduces the level of particle contamination while loading, unloading, and transfer-
ring wafers between process tools. The pod secures the wafer cassette within a Class
10 or better environment and can be transported between stations by manual or



6 Michael A. Rappa

automated methods. Access to the pod occurs through a standardized mechanical
port that Asyst incorporates into various wafer processing tools.

The SMIF-Arm is an integrated system composed of a mechanical port and
robot arm that is within the tool enclosure. The arm lowers the wafer cassette from
the pod through a port and transfers it to the equipment indexer for processing. The
third element of the system is an enclosure that surrounds the process tool and
thereby maintains the tool and wafers in a Class 10 environment — from the pod,
through the port to the tool and back. Figure 3 illustrates a SMIF-equipped process
tool.

In theory, a SMIF tool can provide several advantages for contamination
control in wafer processing. First, it can minimize the effect of organic contamina-
tion on sensitive (especially oxides and film) process steps. Second, it can
minimize the formation and help control the growth of native oxide and other
ultra-thin surface films via encapsulation in inert gases. Third, it can enable the
monitoring and control of the local environment around wafer cassettes. Fourth, it
can minimize long-term storage related deposition and film growth effects.



Room Supply ^

with HEPA



Class 1
Tool Enclosure



Tool Supply
with HEPA



Cl.iss 1000




Process Tool
Fig. 3. Typical SMIF microenvironment process tool.



One additional aspect of the SMIF-Pod system is the ability to electronically
tag each pod with information regarding the wafer lot and its processing sequence
and history. Although this is not a direct concern in contamination control, it is an
extremely useful addition to microenvironment technology that takes advantage of
the pod as a means for inventory control and management (Brain et al., 1987). It
provides convenient access to all information — such as process sequence validation,
real time location of material, feed-forward data and material audit trails — and
automates data acquisition.

Beyond helping control wafer contamination and managing work-in-process,
one of the significant benefits of microenvironment technology is that it is econom-
ical to implement. The capital investment in cleanroom facilities is reduced by



Obstacles to Systemic Innovation 7

the elimination of many special conventional cleanroom design features (Hughes et
al., 1988). These features include extra space and structural support for fans, filters,
motors; wall, floor and partition materials; air conditioning-related vibration
isolation; air showers; garment change rooms; special high volume air conditioning
systems; noise-reduction design elements; and special cleanroom furniture.
Furthermore, the potential reduction in the total annual operating costs for a large
wafer processing facility due to the implementation of microenvironment technol-
ogy is estimated to be about one-third (Tolliver, 1991).

By isolating the process tools in enclosures and the wafers in pods, microenvi-
ronment technology is able to create an ultra clean environment nearest the wafer.
This enables the transport and processing of wafers to occur under carefully con-
trolled conditions that reduce particle contamination. Better control of particle
contamination reduces defects at the wafer surface, which in turn contributes to
improved device yields. Moreover, microenvironment technology greatly simpli-
fies cleanroom construction and operating procedures, thereby reducing capital
expenditures and annual operating costs.



IV. EXPERIMENTAL EVIDENCE

There are three kinds of applications by lead users of microenvironment tech-
nology (Simon 1988): (1) retrofitting of an existing lower class cleanroom, (2)
inserting microenvironment technology into a new or existing higher class
cleanrooms — the "belt and suspenders approach," and (3) optimizing cleanrooms
with microenvironments and minimizing laminar flow zones and clean islands. At
present, the empirical evidence on the effectiveness of microenvironment technol-
ogy is based on a number of pilot-line experiments. Most studies focus on the re-
duction in surface and airborne particle contamination, and on the improvement in
yield resulting from the implementation of microenvironment technology. In most
instances the experiments are based on experience with Asyst's SMIF products.

New Microenvironment Facilities

Two firms operate full-scale microenvironment IC wafer fabrication facilities:
Taiwan Semiconductors Manufacturing Company (TSMC) in Hsinchu, Republic of
China (Tu and Shu, 1990; Shu and Tu, 1992), and Cypress Semiconductor in
Minneapolis, Minnesota, formerly owned by VTC (Workman and Kavan, 1987;
Workman, 1988). Only TSMC has published comparative data on the effectiveness
of microenvironment technology from controlled experiments. Established in
1987, TSMC is the third largest Taiwan-based IC firm, with estimated 1990 rev-
enues of $100 million. The firm provides foundry services using submicron CMOS
technology for application specific ICs and memory products.

At TSMC, the decision to use microenvironment technology is subsumed in one
simple question (Tu and Shu, 1990): "Machine and people in a cleanroom or a
cleanroom in a machine?" The facility is the first to be designed specifically for
the application of microenvironment technology. The conceptual design of the
facility is guided by the following criteria: (1) low cost, quick return on invest-



8 Michael A. Rappa

ment; (2) high reHability; (3) high cleanliness; (4) easy maintenance; (5) easy, fast,
and accurate tracking of work-in-process.

Table 2 shows that TSMC greatly reduced the number of air handling units and
filters. Furthermore, microenvironment technology reduced the volume of clean air
circulating through the cleanroom from 4.9 to 2.4 cubic meters per hour. Airborne
particle measurements inside and outside the SMIF tool enclosures and in the diffu-
sion furnace area show the effectiveness of microenvironment technology for con-
tamination control. Table 3 shows that the number of particles per cubic foot
within the enclosures for all sizes of particles is substantially less than outside the
enclosure.

The mechanical functionality of SMIF tools, recovery time, reliability, and
wafer breakage are also examined by TSMC. Although the evidence is based on
limited operating experience, the data suggest substantial imptovements from mi-
croenvironment technology. In terms of mechanical functionality, SMIF robot arms
were put through 200-cycle runs and 24-hour tests without failure. The recovery
time for SMIF enclosed tools (i.e. the time to achieve operation-level cleanliness
after shutting-down the tool and exposing it to the ambient conditions) in all cases
is found to be less than five minutes. Up-time for SMIF tools registers a level of
98% per month and wafer breakage is measured to be one wafer in 35,000 (Tu and
Shu, 1990).

TABLE 2

Filter and Air Handling Unit Requirements of
SMIF and Conventional Cleanroom



Conventional SMIF



Number of Air Handling Units 103 54

Number of Filters 2,547 1.383

Clean Air Volume 4.9 2.4

(cubic meters per hour)

Source: TSMC (Tu and Shu. 1990)

TABLE 3

Results of Airborne Particle Tests Inside and Outside the
SMIF Enclosure

INSIDE OUTSIDE

ENCLOSURE ENCLOSURE



Particle per cubic foot mean (s.d.) n mean (s.d.) n

particle size >0.1|lm 0.57(0.73) 15 627(1098) 16

particle size > 0.2|im 0.14(0.25) 34 274(420) 16

panicle size > 0.3um 0.11(0.22) 34 117(171) 16

particle size >0.5^lm 0.10(0.22) 34 19(32) 16

Source: TSMC (Tu and Shu, 1990)



obstacles to Systemic Innovation 9

TSMC claims a number of cost and productivity benefits resulting from their
use of microenvironment technology. By reducing the number of air handling units,
TSMC lowered annual operating costs by $1 million. Cleanroom gown expendi-
tures are reduced by $0.5 million per year. Increases in operator productivity are
anticipated as a result of reducing the gown requirements. Moreover, microenvi-
ronment technology enabled the firm to start-up and test some process tools while
installing others, thereby accelerating the ramp-up time to full production. Initial
manufacturing data show a 25% yield improvement compared to the firm's
previous facility, though how much of this increase is attributable specifically to
microenvironment tools is unclear.

Implementing microenvironments at TSMC was not trouble-free. Because mi-
croenvironment technology is a new and radically different approach, process tool
manufacturers have not uniformly adopted the SMIF interface into their equipment.
Therefore, it was the task of TSMC and the system integrator, Asyst, to modify
each of the process tools with the SMIF interface. This increases the length of time
it takes to outfit an entire facility. If the interface was a standard part of process
tools or a vendor option, this would greatly simplify the implementation (Tu and
Shu, 1990).

The construction contractor for the TSMC facility reports an estimate of the
cost benefits from microenvironment technology (Table 4). Given major
reductions in air handling units, filters, clean air volume, electric power consump-
tion, air conditioner capacity, and cleanroom space, the initial capital cost of a
microenvironment cleanroom can be as much as $1000 per square meter less than a
conventional cleanroom. The annual operating costs for the microenvironment facil-
ity are estimated to be $150 per square meter less.

TABLE 4

Potential Cost Saving of SMIF Approach Veisus
Conventional Cleanroom





DOLLARS PER


COST ELEMENT


SQUARE METER


Building construaion


200


Cleanroom system


600


Air conditioners


80


Elearic power


120


Toral initial investment


1000


Annual operating costs


150



Source: Meissner+Wrrst (Simon, 1988)



Retrofitted Microenvironment Facilities

Over a six-month period, NCR ran an experiment to examine the usefulness of


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Online LibraryMichael A RappaObstacles to systemic innovation : an illustration from semiconductor manufacturing technology → online text (page 1 of 3)